Reference no: EM131381134
Refer to the tables at the end of the when answering Questions 1 and 2.
Q1. Figure 1 shows an ALS logic circuit. Estimate:
(a) The current IOL
(b) The delay in a 1-to-0 transition at one of the inputs of GATE 1 appearing as an effect at the output of GATE 5.
(c) The total power consumed by the circuit in a quiescent state.
Q2. (a) Explain with the aid of sketches and by using an example of a specific logic family, what is meant by the term 'noise immunity'.
(b) Explain, if any, the problems associated with interfacing the logic families of the circuits of figure 2(a) and of figure 2(b). For each circuit, if there is a problem of interfacing, give a remedy.
Q3. The block diagram of figure 3 shows a three-stage asynchrononous counter that is used to count a series of randomly occurring input pulses.
The 'Q' outputs of the counter are used to drive a logic circuit that gives the output shown in TABLE 1.
(a) Design the counter using type D flip-flops and simulate your design in PSpice, producing waveforms to confirm the circuit's operation.
(b) Design the logic circuit to realise the desired ABCD outputs and simulate your design in PSpice, again producing waveforms to demonstrate the circuit's operation.
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Input pulse
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D
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C
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B
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A
|
|
0
|
0
|
0
|
0
|
0
|
|
1
|
0
|
0
|
0
|
1
|
|
2
|
0
|
0
|
1
|
1
|
|
3
|
0
|
1
|
1
|
1
|
|
4
|
1
|
1
|
1
|
1
|
|
5
|
1
|
1
|
1
|
0
|
|
6
|
1
|
1
|
0
|
0
|
|
7
|
1
|
0
|
0
|
0
|
|
8
|
0
|
0
|
0
|
0
|
|
9
|
0
|
0
|
0
|
1
|
|
|
etc
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TABLE 1
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COMPARING LOGIC FAMILIES
Performance Specifications
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Typical Single-Gate Performance Specifications
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|
Family
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Propagation Delay (ns)
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Power Dissipation (mW)
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Speed-Power Product pW-s (picowatt-seconds)
|
|
74
|
10
|
10
|
100
|
|
74S
|
3
|
20
|
60
|
|
74LS
|
9
|
2
|
18
|
|
74ALS
|
4
|
1
|
4
|
|
74F
|
2.7
|
4
|
11
|
|
4000B (CMOS)
|
105
|
1 at 1 MHz
|
105
|
|
74HC (CMOS)
|
10
|
1.5 at 1 MHz
|
15
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INTERFACING LOGIC FAMILIES
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Worst-Case Values for Interfacing Considerations for Vsupply of 5.0 V
|
|
Parameter
|
4000B CMOS
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74HCMOS
|
74HCTMOS
|
74TTL
|
74LSTTL
|
74ALSTTL
|
|
V1H (min) (V)
|
3.33
|
3.5
|
2.0
|
2.0
|
2.0
|
2.0
|
|
V1L (max) (V)
|
1.67
|
1.0
|
0.8
|
0.8
|
0.8
|
0.8
|
|
VOH (min) (V)
|
4.95
|
4.9
|
4.9
|
2.4
|
2.7
|
2.7
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|
VOL (max) (V)
|
0.05
|
0.1
|
0.1
|
0.4
|
0.4
|
0.4
|
|
I1H (max) (μA)
|
1
|
1
|
1
|
40
|
20
|
20
|
|
I1L (max) (μA)
|
-1
|
-1
|
-1
|
-1600
|
-400
|
-100
|
|
+IOH (max) (mA)
|
-0.51
|
-4
|
-4
|
-0.4
|
-0.4
|
-0.4
|
|
+IOL (max) (mA)
|
0.51
|
4
|
4
|
16
|
8
|
4
|
|
+ The conversion is that current flowing into a gate terminal is positive and that flowing out is negative.
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