Solution-Draw the layout for 3 input nand gate with minimum

Draw the layout for 3 input nand gate with minimum area

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Reference no: EM131246576

Complete the given assignment.

Enter the details with appropriate explainantions.

Assignment 1
Draw the layout for 3-input NAND gate with minimum area. The schematic of NAND gate using transistors is shown below. (For simulation of schematic and post layout simulation use all signals with rise time as 50 ns and fall time as 50 ns) Give the following data

1. Technology Used :
2. Layout view (image showing all dimension withruler):
3. Extracted view (image):
4. Image of message showing successful DRC
5. Image of message showing successful LVS
6. Dimensions of your layout :

7. Delay

(a). τ^pHL

Input transition	Schematic delay	Post layout delay
A=1, B=1, C=0 to 1
A= 0 to 1, B=1, C=1

(b). τpLH

Input transition	Schematic delay	Post layout delay
A=1, B=1, C=1 to 0
A= 1 to 0, B=1, C=1

8. Maximum delay (τ_d=((τ_pHL + τ_pLH )/2))

(Use maximum value from 7 (a) and 7(b) for this part)

Reference no: EM131246576

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Draw the layout for 3 input nand gate with minimum area

Reference no: EM131246576

Reference no: EM131246576

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