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This problem involves the design of a BCD to binary converter. Initially a three-digit BCD number is placed in the A register. When a St signal is received, conversion to binary takes place, and the resulting binary number is stored in the B register. At each step of the conversion, the entire BCD number (along with the binary number) is shifted one place to the right. If the result in a given decade is greater than or equal 1000, the correction circuit subtracts 0011 from that decade. (If the result is less than 1000, the correction circuit leaves the contents of the decade unchanged.) A shift counter is provided to count the number of shifts. When conversion is complete, the maximum value of B will be 999 (in binary). Note: B is 10 bits.
(a) Illustrate the algorithm starting with the BCD number 857, showing A and B at each step.
(b) Draw the block diagram of the BCD-to-binary converter.
(c) Draw a state diagram of the control circuit (three states). Use the following control signals: St: start conversion; Sh: shift right; Co: subtract correction if necessary; and C9: counter is in state 9, or C10: counter is in state 10. (Use either C9 or C10 but not both.)
(d) Write a VHDL description of the system.
A hybrid communication system uses both AMSC and FM. The information signal a(t) is first AMSC modulated with the subcarrier frequency 1000 Hz. Then it passes through an FM modulator with the carrier frequency 10Mhz.
write sets of state equations for DFII and its transpose, cascade, and parallel forms. Also write the corresponding output equations.
Derive a minimal state table for an FSM that act as four bit parity generator. For every four bits that are observed on the input w during four consecutive clock cycles, the FSM generates the parity bit p = 1
When placed in series a coil and capacitor resonate at a fequency of 2251Hz and when placed in parallel they resonate at a frequency of 2228Hz. At parallel resonance it is also found that a current of 0.005A flows from the supply when the supply i..
For a modified 2-stage cascade in which one of the resistors is decreased to kR (k51), find a process to calculate what the frequency becomes. For what value of k does f y dB of the modified 2-stage 0.95 cascade have a value 2aR ?
The Switch in the circuit shown below has been open for a long time. It is closed at time t=0. - Find i(t) for t>=0.
Use this table of part c to determine the mean, median, and mode of the grouped data. Compare your results with those in part A, and comment. E. use the frequency table of part C. to determine the variance and the standard deviation of the groupe..
Find the transfer functions relating each of these outputs to Vin, and determine which is which.
You have an amplifer with a nominal open-loop gain of 1000 (A = 1000), but the variance in the gain is 20% (meaning that the open-loop gain ranges in value from 800 to 1200). You want to use feedback to try to desensitize the gain.
Derive Eigenvalue equation for the Transverse magnetic modes in a symmetric waveguide.
A 0.100 mA electron beam with kinetic energy 54 eV enters a sharply defined region of lower potential where thekinetic energy of the electron is increased by 10 eV. What current is reflected at the boundary
A cell phone transmits voice signals on a carrier. the transmissions lie inbetween 900MHz to 900.03MHz. What minimum sampling rate should be choosen so that the transmisions will be recoverable from the digital samles
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