Draw a block diagram and write a vhdl description

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Reference no: EM131368294

A synchronous (4-bit) up/down decade counter with output Q works as follows: All state changes occur on the rising edge of the CLK input, except the asynchronous clear (CLR). When CLR = 0, the counter is reset regardless of the values of the other inputs.

(a) Write a VHDL description of the counter.

(b) Draw a block diagram and write a VHDL description of a decimal counter that uses two of the above counters to form a two-decade decimal up/down counter that counts up from 00 to 99 or down from 99 to 00.

(c) Simulate for the following sequence: load counter with 98, increment three times, do nothing for two clocks, decrement four times, and clear.

Reference no: EM131368294

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