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Consider a regenerative Rankine cycle with a 600C and 4-MPa throttle, a 5-kPa condenser, and an open feedwater heater at 500 kPa. Turbine efficiencies are 85%.
Neglect pump work.
(a) Draw labeled, coordinated T-s and flow diagrams.
(b) Determine the fraction of the throttle mass flow that passes through the extraction line.
(c) Calculate the turbine work per unit mass at the throttle.
(d) Calculate the cycle efficiency, and compare it with the simple-cycle efficiency.
(e) Calculate the heat rate.
A micrometer caliper is used to measure the diameter of a bolt and a reading of 0.768 inches is obtained. Based on this measurement, find the smallest possible diameter and the largest possible diameter.
Consider a PCM-TDM system in which 24 signals are to be processed. Each signal has a baseband bandwidth of 3 KHz. The sampling rate has to be 33.3% higher than the theoretical minimum, and 8 bits are to be used.
Three Single-Phase two-winding transformers, each rated 25 MVA, 38.1/3.81 kV, are connected to form a three-phase Wye-Delta bank with a balanced Y-connected resistive load of 0.6 ohms per phase on the low-voltage side.
What is the maximum message bandwith for which the system operates satisfactorily? Determine the output signal to quantizing noise ratio when a full-load sinusoidal modulating wave of frequency 1 MHz is applied to the input.
Two charges are held fixed in an x-y plane. Charge Q=-1*10^-9 C is located at the origin, q=3*10^-9 C is located at (0,2). Determine the voltage (v_ba) between point 'b' located at (3,0) and point 'a' located at (1,0).
Use the simulation timing diagram to compare the worse case time to do an operation with your ALU with the worst case using the 74LS381. State which operation takes the longest and list the time required for both ALU's.
Describe what precautions you will take in designing the analog front end of the instrument before you perform the sampling for DSProcesing. Justify your claims by using engineering arguments.
A three-phase generator is Y-connected. It has phase voltages of 277 V. A delta-connected load is attached to the lines coming from the generator. Each phase of the load has an impedance of 9/41
"Divide by 3 clock with 50% duty cycle" is the most commonly asked ASIC design question. This solution gives a simple design in which only 1 counter is required which works only on positive edge of the clock.
A 50 ohms lossless transmission line is to be connected to a load of 25 ohm. Use a lamda/4(quarterLamda) length of line of unknown impedance between the load and the 50-ohm line to match it,
draw out a schematic that implements a 3-bit XOR gate, but consisting of only 2-bit NAND gates. Your schematic should have from 8-10 NAND gates, but NO other logic function such as OR, AND, INV gates can be in your final design.
Suppose we have a causal LTI system with rational system function H(s). We don't know H(s), but we do have the following information: i. When the input to the system is x(t) = u(t), the output y(t) is absolutely integrable.
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