Design the circuit such that the power dissipation

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Reference no: EM131228070

Consider the NMOS inverter with depletion load in Figure 16.7(a). Let V_DD = 1.8 V, and assume V_TND = 0.3 V and V_TNL = -0.6 V.

(a) Design the circuit such that the power dissipation is 80μW and the output voltage is v_O = 0.06 V when vI is a logic 1.

(b) Using the results of part (a), determine the transition points for the driver and load transistors.

(c) If (W/L)_D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is v_O when v_I is a logic 1?

Reference no: EM131228070

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