Design the binary counters for the dimes and nickels

Assignment Help Electrical Engineering
Reference no: EM131470118

Question 1

An Arithmetic Logic Unit (ALU) is at the heart of all computers as well as most digital hardware systems. It is a combinational network that performs logical and arithmetic operations.

An n-bit ALU typically has two input words A and B, each of which denoted by A=An-1An-2...Ao and B = Bn-1Bn-2...Bo. The output word is denoted by F = FnFn-1...Fo, where the high order output Fn is actually a carry-out.

In addition, there is a carry-in input Co. Besides data inputs and outputs, an ALU must have control inputs for specifying the operations to be performed. The control inputs include a mode selector, M, and operation selector inputs, So and S1. The mode selector is needed to decide whether logical or arithmetic operation is to be performed and the operation select inputs are required to determine which particular logic or arithmetic function is to be performed. The specification of a simple ALU bit slice, that is the behaviour of a single bit of an ALU, is given in Table 1. The operations are broken down into three sections: logical operations, arithmetic operations where the carry-in is 0, and arithmetic operations where the carry-in is 1.

Based on the specification, design an 8-bit ALU. Your design should begin with a 1- bit slice of the ALU and then cascade them to build the desired 8-bit ALU. Note the single bit slice will have six inputs: Ai, Bi, Ci, M, S1, and So, and two outputs: Fi and Ci+1 (carry-out). Your design should include your choice of circuit implementation, simulation and verification. For the purpose of this assignment, it will be suffice to show the simulation and verification of the 1-bit slice of the ALU. Your design should aim at achieving optimized implementation and include calculation of gate input cost.

 

Function

comment

M=0, Co=X S1              So

0        0

0        1

1        0

1        1

Logical Bitwise Operation

 

Fi = Ai

Fi = NOT Ai

Fi = Ai XOR Bi Fi = Ai XNOR Bi

 

M=1, Co=0 S1              So

0         0

0         1

1         0

1         1

Arithmetic Operations

 

F = A

F = NOT A F = A + B

F = (NOT A) + B

 

M=1, Co=1 S1              So

0         0

0         1

1         0

1         1

Arithmetic Operations

 

F = A + 1

F = (NOT A) + 1 F = A +  B + 1

F = (NOT A) + B + 1

Increment B - A

Table 1: Specification for ALU

Question 2

You are to design a combinational circuit block as part of a larger system that makes change from quarters (25 cents coin). There is a large reservoir of dimes (10 cents coin) and another one of nickels (5 cents coin). Two binary counters keep track of the number of dimes and nickels in each. The circuit block should work as follows:

It takes the low-order of bits of the dimes counter and the nickels counter and generates the number of dimes and nickels to give as change. In general, dimes should be given before nickels. For example, if there are at least two dimes left, these should be given with a single nickel, rather than five nickels. There is definitely a possibility that no change can be given before the reservoirs are (almost) exhausted of coins and "a no change available" sign should be illuminated. You do not need to design the binary counters for the dimes and nickels. But you will need them as inputs.

Although the vector length of the binary counters is not critical, for the purpose of this design you may assume the vector length of the binary counters as four. Your design should include your design procedure, choice of implementation, simulation. The gate input cost must be calculated.

Verified Expert

The assignment consisted of 2 VHDL codes. I have completed one of them. Actually my software is not working. So, I am unable to run the second one. I am trying. I will send the second code as soon as the software responds.

Reference no: EM131470118

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Reviews

inf1470118

5/12/2017 5:13:55 AM

Thanks for the final solution, it is now complete work as per the requirements. Thanks for being straightforward, it is somewhat more costly however I have attempted to work with different organizations and have not been effective.

inf1470118

5/12/2017 5:12:11 AM

Please look at the marking guideline. The only thing added from the last file you sent me is a short explanation. You can't just write VHDL code. It needs to have a schematic with all the logic gates uses eg(AND,OR,XOR etc), so please do the questions with logic gates not VHDL code.It will need to have an optimisation step where you use a k-map to reduce the boolean function. It will need the input gate cost. It will need screen shots of the wave form and a Verilog test file from xilinx. All of this is in the guideline file I attached. It tells you exactly what to do and how much marks are for each step. Such as Design approach is 10 marks, Formulation is 10 marks etc. Please just follow the guideline file called (ELEC2141 assignment marking guideline).

len1470118

4/22/2017 2:53:56 AM

• Your assignment solutions are to be submitted at the assignment box at the school office. • Attach completed and signed assignment submission form as a front page to your submission. • For each of the design question, you may use Xilinx ISE or any other appropriate CAD tool to simulate and verify your design. • Attach all design and simulation materials such as schematic diagram (or HDL), simulation output and testing fixture.

len1470118

4/22/2017 2:53:33 AM

3. Optimization: (10 marks) • Show all K-maps used and indicate clearly which essential prime implicates or prime implicates are selected in your optimized Boolean expression (8) o If the Boolean expression is not correct or not optimized correctly, 1mark will be deducted per expression • If multi-level circuit implementation is employed, show the optimization steps • Indicate GIC of your optimized design (2) 4. Circuit implementation (10 marks) • Draw logic diagram. It has to be neat and clearly labelled ( inputs and outputs) (7) • Indicate clearly your particular choice of implementation ( NAND only, NOR only etc) (3) 5. Verification (10 marks) • Draw the schematics of your implementation in Xilinx ISE • Write the Verilog test file ( attach the file) -- (5) • Include the simulation result from Xilinx (attach the file). It has to clearly show the waveforms for all inputs and output. – (5)

len1470118

4/22/2017 2:53:28 AM

Assignment marking guideline: Assignment I has two design problems. Each of them will be marked out of 50. The marking breakdown is outlined below 1. Design approach: (10 marks) • Explain clearly the design approach ( are you using functional blocks? hierarchical design? Five or four variable k-maps?) (4) • Any assumptions made must be explicitly stated (1) • You may concisely re-write the specification including your design assumptions if needed (5) 2. Formulation: (10 marks) • Draw any truth table required and clearly indicate input and output columns (10) o If appropriate “Do not care conditions” are not used, two marks will be deducted o Wrong Truth table – deduct 5 marks • Show any hierarchical block diagram if used. • If Boolean function is generated directly from the specification, explain how you arrive at the Boolean function and clearly indicate the function. (10) o Boolean function – 5 marks o Correct explanation – 5 marks

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