Design four-bit shift register with paralel load using d-ff

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Reference no: EM13294624

Design a four-bit shift register with a paralel load, usingD-flip-flops. There are two control inputs:shift and load. Whenshift t=1, the contents of the register are shifted by oneposition. New data are transferred into the register when load=1and shift=0. if both control inputs are equal to 0, the contents ofthe register do not change.

Reference no: EM13294624

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