Reference no: EM132930956

ELEC4720 Programmable Logic Design - The University of Newcastle

PROBLEMS.

1. Design and implement a 5 stage pipelined processor with 18 bit wide instructions, and data- word width of your choice. In addition, test your processor on dev board using one or more appropriate test programs. Together these programs should be rich enough in the sense that
• it should include the common programming language constructs like standard arith- metic, logic, and shift oprtations, conditional statements (if-then-else type), loops, etc.
• it should be sufficient to demonstrate that all the main hardware components of your design is working properly
If your design for this part is different from your design in Part 2.2, then please update your report with the
• Instruction set along with the binary codes
• Instruction encoding/decoding logic
• Discuss various tradeoffs made in your design to optimize the following:
- Instruction coverage
- Dataword width,
- Number of registers,
- Memory adressing scheme (byte or word addressable, base/offset based addressing)
- Memory address and offset range
- Jump offset range
- Branch offset range
• Show the data path needed to implement your design
• Discuss the the control signals and their logic

MARKING CRITERION.
• Processor coverage (14)
- ALU instructions with register operands (2)
- Multiplication/Division instructions with register operands (2)
- Shift instructions with register operands (2)
- ALU instructions involving constant operands (2)
- Branch instructions (2)
- Jump instructions (2)
- Complexity of memory read and write instruction implementation (2)
• Hazard management (15)
- Read after write hazard (5)
- Memory load hazard (5)
- Branch hazard (5)
• Testing (21)
- Capability of the test methodology to ensure the bug-free hardware (7)
- Final demo program on the dev board (14)
• Speed (10)
- The mark will depend on how fast your processor can be clocked on dev board. Note:
• Please document all the test programs and strategies used during the course of hardware
development. This should also include the test programs used for testing various parts of the design while the hardware is being developed.
• If you are unable to demonstrate the CPU on the dev board then you will not get the full marks. The mark will depend on our examination of your code, and testing on modelsim.
• While working on the dev board start with a slow clock like 1 Hz. Then gradually increase the clock speed and test how fast you can clock your processor. For a good design you should be able to clock your CPU with a 50 MHz clock.