Reference no: EM133594018
Introduction to Logic Design
Design an amplifier
Design Project
For this project, the cadence simulation examples and the 45 nm device model are shared on Canvas. Using the given 45 nm CMOS technology, design an amplifier (with more than one stage) that satisfies the listed requirements:
*If you plan on working individually
(Gain-bandwidth product) GBW > 220e9 Rin > 500 kΩ
Rout < 150 Ω
DC Power Consumption < 18 mW Output Voltage Swing > 2.4 Vpp Vdd < 3.6V
*If you plan on working in a group of two people
GBW > 270e9
Rin > 700 kΩ Rout < 120 Ω
DC Power Consumption < 18 mW Output Voltage Swing > 2.5 Vpp Vdd < 3.6V
10% Additional Bonus Items (for both individual and group projects):
Phase Margin > 50 degree Op-Amp CMRR > 70 dB
Important Point: For all circuits except the current mirrors and biasing circuits, use transistors with minimum width of 5 μm. The transistor models in this library have some wrong parameters for small width values.
If you decide to work in group of two people, please send me an email with your group member names by 10/30/2023. Upon not receiving an email from you, I would assume that you will work on the project individually.
The project reports are due on 12/08/2023 and should include clear snapshots of the schematics including the device sizes, resistor values, capacitor values, and DC voltages. You should also include the analytical calculations and design steps that led to your final design. The required simulation results including sp analysis, DC and transient simulations, ac simulations should be included to justify the performance specifications.
Please also make a table of performance at the end of your report which reflects the achieved simulation results.