Reference no: EM13263895
Design a synchronous 2-bit, binary, up-counter using the following specification: The counter has five inputs ( not including the clock) and three outputs. The inputs are CLR ("Clear"), LOAD, COUNT, LB and LA. CLR takes precedence over LOAD, which in turn takes precedence over COUNT. The outputs are B, A, and RCO. The output RCO goes high only when the counter has reached the highest value ("11" in this case).
a) Draw the interface schematics of this counter
b) Decide how you can implement this using flip-flops. (You may use D, JK, or T flip-flops.)
c) Draw the implementation schematics.
d) Draw a timing diagram to illustrate the correct opeartion of this counter, as it goes through the entire sequence and wraps around. On this timing diagram, you need to display the waveforms for all inputs and outputs. You need to show how you achieve "reset" on this counter in the beginning, how the counter advances and then wraps around. (Through this excises, you will gain a better understanding of what signals are aserted exactly when.)
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