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Give the size, in octets, of the ATM cell. How much is header, how much is payload? Why must we be careful when we specify this? Describe at least two of the functions of the HEC in the ATM header ? Define packetization delay. How did packetization delay force ATM designers to shorten cell payload as much as possible?
Two p+-n abrupt junction diodes are made from silicon and are identical except that the donor levels in the 2 diodes are ND_1=10^15 and ND_2 = 1x10^17 cm-3.
Given y[n]=x[n]+y[n-1]+y[n-2] find the unit-step response of this system using the transfer function method, assuming zero initial conditions.
A 3.3 kV, 20-pole, 50 Hz, 3-phase, starconnected induction motor has a slip-ring rotor of resistance 0.025 W and standstill reactance of 0.28 W per phase. The motor has a speed of 294 rpm when full-load torque is applied.
A transistor amplifier has a midband gain of -120, a high cutoff frequency of 36KHz, and a bandwidth of 35.8 KHz. In addition, the actual response is also about -15 dB at f=50Hz. Write the transfer function Av for the amplifier.
A silicon diode has a doping profile such that ND = ax3. What is the depth of the junction assuming the p side is uniformly doped with NA per cubic cm. Assume the x origin is at an ideal ohmic contact on the n side of the diode.(assume T=300K).
If Vid is 20-mV peak-to-peak sine wave applied in a balanced manner but superimposed on Vcm = 0.5 V, what is the lowest value that Vdd must have to ensure saturation -mode for Q1 and Q2 at all times. Assume Vt = 0.5 V.
What is the time constant of the circuit with S1 closed and what is the eventual steady-state current with S1 closed - what is the value of the circuit current at the first instant S1 is closed?
Does the Doherty amplifier of Figure operate properly if the input is driven by an ideal voltage source? Explain your reasoning.
What is Intermediate switch , its construction and how it works?
How do you draw a schematic of a circuir that implements any of the following: a circular left or a right shift of 0-3, or a logical left or right shift of 0-3
Design a combinational circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than A. The circuit has one output X, so that X = 1 if A = B.
Find the output y[n] of an LTID system specified by the equation 2y[n+2] - 3y[n+1] = y[n] = 4x[n+2] - 3x[n+1]if the initial conditions y[-1] = 0, y[-2] = 1, and the input x[n] = (4)^-n u[n]
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