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A coil wound on a magnetic core is excited with the followingAC voltage sources: a) 100 volts, 50 Hz, b) 110 volts, 60 Hz.Compare the hysteresis losses and eddy current losses (ratio) forthe two different sources. For the hysteresis losses, assume n =2.
A balanced three-phase load is connected to a balanced three-phase supply via a transmission line. What must be the readings on the two wattmeters, the ammeter, and the voltmeter
A serial RLC circuit is connected to a 24 DC voltage source att=0: The output y(t) is the voltage on the capacitor one sideof which is connected to the ground. L= 1 Henry, R=2.5 Ohms and C= 1 Farad. The circuit is at restfor t
A line charge of infinite lenght lies along the z axis and carries a uniform linear charge density of ρl C/m. A perfectly conducting cylindrical shell, whose axis is the z axis, surrounds the line charge.
Create a non-inverting op amp circuit to obtain Vout = 12 V if R2 (RF) = 1100k-ohm and Vin =1V . Open up the attributes window of the op amp (click on the op amp symbol) and verify that VPOS = +15V and VNEG = -15V. Do not change any other attribut..
Phosphorous is an n-type dopant in Si since it introduces extra electrons to Si (an P atom has 1 more valence electron than Si). It is widely used in making semiconductor devices (p-n junctions for example).
The load on a 460-v, 60-Hz, Y-connected, balanced three phase source consists of three equal Y connected impedance of 100-j100 Ohms and three equal delta-connected impedance of 300-j300 Ohms.
The amplitudes of two signals X and Y have joint pdf: fXY (x,y) = e^(-x/2)*y*e^(-y^2) for x>0 , y>0. (a) Find the joint CDF (b) Find P [sqrt(x) > y] (c) Find the marginal PDFs (d) Determine if X and Y are independent.
Three series impedances of 33 ohm, 6j ohm and 87j ohm W are connected in star across a 220-V, three-phase supply. Sketch the circuit diagram and the phasor diagram (Take Vab as reference). Calculate the total power in kW.
Create a circuit of three level sensitive D latches connected in series(the output of one is connected to the input of the next). Use a timing diagram to show how a clock with a long high time can cause the value at the input the first D latch
A box contains a shipment of N (N>4) computer chips, of which four are defective. Four chips are randomly selected and examined as to wether or not the chips are defective. Describe the sample space for this experiment.
A CMOS clocked SR flip-flop uses a technology with unCox = 100 uA/V^2, upCox = 25 uA/V^2, VDD = 2.5V, Vtn = -Vtp = 0.5V and the total capacitance at the output nodes equals 15fF. The inverter threshold voltage VM = 2.5V.
Given a 100 MHz clock signal, derive a circuit using D Flip Flops to generate 50 MHz and 25 MHz clock signals. Draw a timing diagram for all three clock signals, assuming reasonable delays.
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