Also called the parallel A/D converter, the circuit of Figure is the easy to understand. This is made of a series of comparators, each one comparing the input signal to exclusive reference voltage. The comparator outputs linked to the inputs of a priority encoder circuit, which then produces a binary output. Following illustration of Figure illustrates a 3-bit flash ADC circuit. And, of course, the encoder circuit itself may be built from a matrix of diodes of Figure, demonstrating just how simply this converter design can be constructed. Not only is the flash converter the simplest in terms of operational theory, however it is the most efficient of the ADC technologies in terms of speed, being restricted only in comparator and gate propagation delays. Unluckily, it is the most component-intensive for any given number of output bits. This three-bit flash ADC attains eight comparators. A four-bit version would need 16 comparators. With each added output bit, the number of needed comparators doubles. Assuming that eight bits is generally considered the minimum necessary for any practical ADC
(256 comparators needed), the flash methodology quickly illustrated its weakness. An additional benefit of the flash converter, frequently overlooked, is the ability for it to produce a non-linear output. Along with equal-value resistors in the reference voltage divider network, each of the successive binary count represents the same amount of analog signal increase, by providing a proportional response. However, for special applications, the resistor values in the divider network can be made non-equal. It gives the ADC a custom, nonlinear response to the analog input signal. No other ADC design is capable to grant this signal-conditioning behaviour with just a few component value changes.
Figure: Parallel ADC