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CMOS NOT Gate:
Figure (d) represent the CMOS NOT Gate where TN is NMOS FET and TP is PMOS FET. Whereas input is at 0 V, TP is on, TN is off and the output is at Vcc. But when input is at Vcc, TP is off and TN is on and the output is at 0 V. So the CMOS circuit of Figure (d) behaves as NOT gate.
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