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CMOS NAND Gate:
Figure (e) represents the CMOS NAND Gate where the TN1 and TP1 have the same Input1 and TN2 and TP2 has the same Input 2. When Input 1 = Input 2 = 1, TN1 and TN2 is on and TP1 and TP1 are off. Thus the output is at 0 V. Whereas Input 1 = Input 2 = 0, TN1 and TN2 is off and TP1 and TP1 are on. Therefore the output is at Vcc. For the case when either one of the inputs is 0, one of the PMOS FET shall be on and therefore the output will be at 1 V. Therefore the CMOS circuit of Figure (e) behaves as a NAND Gate.
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