What is verilog case 1, Computer Engineering

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What is verilog case (1) ?

wire [3:0] x;

always @(...) begin

case (1'b1)

x[0]: SOMETHING1;

x[1]: SOMETHING2;

x[2]: SOMETHING3;

x[3]: SOMETHING4;

endcase

end

Case statement walks down the list of cases and executes first one that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that would get executed (or selected by the logic).

 


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