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What is the hardware support required to implement paging?
Each operating system has its own techniques for storing page tables. The majority allocates a page table for each process and a pointer to the page table is stored with the other register values in the process control block.
The hardware execution of the page table can be done in several ways. In the simplest case the page table is executing as a set of dedicated registers. These registers must be built with very high-speed logic to make the paging-address translation efficient.
The use of registers for the page table is adequate if the page table is reasonably small. For other cases the page table is kept in main memory also a page table base register (PTBR) points to the page table. Changing page tables needs changing only one register substantially reducing context-switch time.
Though the standard solution to this problem is to use a fast-lookup, special, small hardware cache called translation look-aside buffer (TLB). The TLB is an associative high speed memory. Every entry in the TLB consists of 2 parts: a value and a key. Only some TLB's stores address-space identifiers (ASID's) in an every entry of the TLB. An ASID uniquely identifies every process and is used to provide address space protection for that process. While TLB attempts to resolve virtual page numbers, it makes sure the ASID for the currently running process matches the ASID associated with the virtual page.
Another solution then would be to keep a pool of threads. Whenever a new task arrives, the system would simply get a thread from pool and set that thread to work on the given task.
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