Already have an account? Get multiple benefits of using own account!
Login in your account..!
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
Throughput Throughput of a pipeline may be defined as number of results which have been achieved per unit time. It can be referred as: T = n / [m + (n-1)]. c = E / c Th
Development of information system must be considered as capital investment: The developer of an information system must think about different solutions of a particular problem and
Q. Show the Classification of Printers? Printers can be classified on following bases: a) Impact: Impact printers print by impact of hammers on ribbon (for example Dot-Matri
Interconnection Network (IN): IN performs data exchange between the PEs, manipulation functions and data routing. This IN is under the control of CU.
How many types of stages include in process of data mining? The process of data mining comprised three stages as given below: a) The initial exploration b) Model buildin
In a particular exchange during busy hour 1200 calls were offered to a group of trunks, during this time 6 calls were lost. The average call duration being 3 minutes Calculate
What is text editor? It is used for entering and editing application programs. The user of this program interactively implements command that permit statements of a source prog
Example of Weight training calculations: Through having calculated all the error values associated with such each unit like hidden and output then we can now transfer this inf
RISC Approach - computer architecture: The RISC processors only use easy instructions that can be executed within one clock cycle. therefore, the "MULT" command discussed abov
Software Aspects: Software is a generic term covering the concepts, procedures and instructions which enable computer systems to do useful things. Usually, software is conceiv
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd