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Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
Width elements of ports, wire or reg declarations require a constant in both LSB and MSB . Before Verilog 2001, it's a syntax error to specify a function call to evaluate the value of these widths. For instance, the below code is erroneous before Verilog 2001 version.
reg [ get_high(val1:vla2) : get_low (val3:val4)] reg1;
In the above illustration, get_high and get_low are both function calls of evaluating a constant result for MSB and LSB correspondingly. However, Verilog-2001 allows the use of a function call to evaluate LSB or MSB of a width declaration.
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