In the past there was a large gap between speed of a memory andprocessor. So a subroutine execution for an instruction for illustration floating point addition may have to follow a lengthy instruction sequence. Question is; if we make it a machine instruction then just one instruction fetch will be needed and rest will be done with control unit sequence. So a 'higher level' instruction can be added to machines in an effort to improve performance.

Though this supposition is not very valid in present era where Main memory is supported with Cache technology. Cache memories have decreased the difference between memory and CPU speed and so an instruction execution by a subroutine step may not be that difficult.

Let's explain it with help of an illustration:

Suppose floating point operation ADD A, B needs the subsequent steps (presuming the machine doesn't have floating point registers) and registers being used for exponent are E1, E2, and EO (output); for mantissa M1, M2 and MO (output):

• Load exponent of A in E1
• Load mantissa of A in M1
• Load exponent of B in E2
• Load mantissa of B in M2
• Compare E1 and E2

-  If E1 = E2 then MO ← M1 + M2 and EO ← E1

Normalise MO and adjust EO

• Result will be contained in MO, E1

Else if E1< E2 then find the difference = E2 - E1

• Shift Right M1, by difference
• MO ← M1 + M2 and EO ← E2
• Normalise MO and adjust EO
• Result is contained in MO, EO

 Else E2 < E1, if so find the difference = E1 - E2

• Shift Right M2 by difference above
• MO ← M1 + M2 and EO ← E1
• Normalise MO and adjust E1 into EO
• Result is contained in MO, EO

 Store the above results in A

 Checks overflow underflow if any.

If all above steps are coded as one machine instruction then this simple instruction will need many instruction execution cycles. If this instruction is made as part of machine instruction set as: ADDF A,B (Add floating point numbers A and B and store results in A) then it would just be a single machine instruction. All above steps needed will then be coded with help of micro-operations in form of Control Unit Micro-Program. Soonly one instruction cycle (though a long one) may be required. This cycle will need only one instruction fetch. While in the program memory instructions will be fetched.

Though faster cache memory for data and Instruction stored in registers can create an almost similar instruction execution environment. Pipelining can further increase such speed. So creating an instruction as above may not result in faster execution.