Requirements for cache simulator, Computer Engineering

Using your cache simulator and using smalltex.din as your memory trace determine the total miss rate, compulsory miss rate, capacity miss rate, and conflict miss rate for the following cache configurations by varying the inputs as suggested below. Examine your results/observations in each case and compare them to a run using dineroiv (a commercial cache simulator). This exercise is to validate the operation of your simulator compared to a commercial simulator and to familiarize yourself with the results that occur for each architecture. Comparing your results with dinero validates your cache simulator. Answering the questions below will help you gain a deeper understanding of the function/operation of caches with respect to various trace files and any patterns within trace files.

1. Keeping block size constant (say 64 bytes) compare the different replacement policy's with several cache sizes (say 16, 64, 256, 512KB) and associativity (direct, 2-, 4-, 8-way, fully associative). Note the trends and confirm your observations from your cache simulator with dineroiv

2. Keeping replacement policy constant (for random and then LRU) and block size constant (say 64 bytes) collect total, compulsory, capacity, and conflict miss rates for each of the following cache organizations and compare with the results from dineroiv.:-

3. Cache sizes 4, 16, 64, 128, 256, 512 KB,

4. Degree of associativity 1-way, 2-way, 4-way, 8-way, fully.

5. To ensure that your cache simulator is fully operational you should be able to perform the following:-

a.  Accept any block sizes from 2 bytes to 2048 bytes,

b.  Accept any cache size from 1Kb to 8MB,

c.  Accept either LRU or random replacement policy for each run,

d.  Accept the following degree of associativity, Direct, 2-way, 4-way, 8-way, and fully associative.

6.  Additionally, to help you anaylze the operation of caches with a trace file be prepared to perform the following:-

(a) What is the largest address in smalltex.din?  (Write a small C program to find this value is it will affect your declarations ó int, long long, unsigned,...etc.)

(b) Is there a pattern in the trace file - if so, estimate the occurrences of the pattern and how it will impact (validity, fair test, etc) on the performance of a cache simulator. (Hint. Again a small C program that can find a given  address and outputs the line number for each occurrence)

(c) Also, consider the following: if a trace file was to be constructed simply by generating random numbers between 0 and MAX RAM-mem (say 16MB), would this be a better/best way to test:-

a.  Cache simulator,

b.  A possible real program?   {Remember principle of locality as iy applies to real data!!!}

Posted Date: 2/28/2013 2:57:19 AM | Location : United States







Related Discussions:- Requirements for cache simulator, Assignment Help, Ask Question on Requirements for cache simulator, Get Answer, Expert's Help, Requirements for cache simulator Discussions

Write discussion on Requirements for cache simulator
Your posts are moderated
Related Questions
How do transmission bridges help in satisfying the connectivity? A usual transmission bridge is demonstrated in figure. The series capacitance and the shunt inductances of

Syntax and Semanticsx and Semantics for First-order logic - artificial intelligence: Propositional logic is limited  in its expressiveness: it may just represent true and false

Use the colon operation to create a vector x of numbers -10 through 10 in steps of 1. Use matrix operations to create a vector y where each element is 5 more than 2 times the corre

Scenarios encapsulate the Vuser Groups and scripts to be implemented on load generators at run-time. Manual scenarios can deal out the total number of Vusers between scripts bas

A distributed network configuration in which all data/information pass through a central computer is (A)  Bus network                            (B) Star network (C)  Rin

how to breadboARD THE 4 BIT COMPARATOR

The conflict between too hot and too cold or too slow and too fast can be resolved using don't care states. Don't care states are used when i) the state of the output is not

Single Instruction and Single Data stream (SISD) In this organisation, sequential implementation of instructions is executed by one CPU having a single processing element (PE

State the term in detail $strobe $strobe. This task is very similar to $display task except for a slight difference.  If many other statements are executed in same time unit as

Appropriate Problems for ANN learning - artificial intelligence-  As we did for decision trees, it is essential to know when ANNs are the correct representation scheme for the