1.1 A Few Notes:

1. Please test your program with various inputs prior to submission.

2. All group members must understand the entire project for interactive grading. Equal grades are not guaranteed.

3. Get started early! This will take a surprising amount of time.

2 Cache Design

Both caches take as input a filename from the command line. The file specified by the filename will be an ASCII file with each line in the following 7-byte format;

Byte(s) Function

1 - 2 16 bit address

3 Read/Write indicator

4 - 7 32 bits of data to be stored in the cache.

This byte will be all 0's in the case of a read, and all 1's in the case of a write.

Upon a read operation the data segment of the 7-byte format will be ignored. However when a write occurs the data will be written into the specified byte and the dirty bit may or may not be set. Input files will be an ASCII file with each line in the above 7 byte format and each entry given on separate lines. For ease of creation the input file will be in hex, for example:

Which would appear in the input file as:

002C FF FD23D83F

0080 FF 4E42732A

Address Read/Write Data

002C FF FD23D83F

0080 FF 4E42732A

002C 00 28E5732C

002C 00 28E5732C

Where the first two lines in this example would write data to the designated addresses, and the third line would tell cause your cache to be read and the data bytes would be ignored at this point. The cache produces as output a file named out.txt, which will contain the addressed data for a read operation, a HIT output indicating whether the requested item was found in the cache, and the dirty-bit. These pieces of information should be separated by a space, and for each of the read inputs there should be a line in the output file Thus for the example above we will have a one line output file that would appear as follows:

FD23D83F 1 1

2.1 Direct Mapped Cache

To begin this project you are to implement a 512 byte Direct-mapped cache with a line size of 8 bytes and word size of 4 bytes. Your cache is to be byte addressable. The cache must support a read operation (reading a byte from the cache) and a load operation (loading new bytes of data into the cache). In the case of a failure to read you will report a miss, for a success a hit is reported.

2.2 Set Associative Cache

After implementing the Direct-mapped cache you will alter it (in a separate _le) in order to implement an 256-byte, 4-way set associative cache. Additionally the cache must have a replacement policy; you will implement a least recently used (LRU) replacement policy for blocks. The other specifications will remain the same, you must support read and load operations, and a LRU replacement policy for blocks.

2.3 Additional Specifications

_ The cache will not be implemented in Quartus!! Instead you will implement it in C/C++ or python.

If you choose to implement in C or C++ you must provide a Make file and your code must compile on the CSIF machines.

_ the Direct Mapped file will be named DMcache (with the appropriate extension).

_ the Set Associative Cache will be named SAcache (with the appropriate extension).

_ There will be NO interactive grading, each portion of the project is pass or fail and worth 50% of the project grade.