Post interrupts - computer architecture:

Post interrupts

• Exact interrupts
• examine interrupt bit on entering WB
• Longer latency

Handle immediately

•   interrupt may take place in order different from sequential CPU
•   not completely precise
•   May cause implementation headaches!

Other complications

•   odd bits of state (for instance :CC)
•   early-writes (for instance auto increment)
•   out-of-order execution
•   dynamic scheduling
•   instruction buffers and prefetch logic

 

 

 

Posted Date: 10/13/2012 7:16:40 AM | Location : United States

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