The easiest way to approach pipelining is to regard as the three stage fetch, decode and execute instruction execution cycle outlined earlier. There are times during each of these sub cycles of the main cycle where the main memory is not being accessed, and the CPU could be regarded as ''idle''. The idea, hence, is to begin the fetch stage for a second instruction while the first stage is being decoded. When first instruction one is being executed and second instruction is being decoded, a third instruction can be fetched.

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