Interrupt signal interconnection network (isin), Computer Engineering

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Interrupt Signal Interconnection Network (ISIN):

When a processor wish to transmit an interruption to another processor, then this interrupt initially goes to ISIN, by which it is passed to the target processor. In this method, synchronisation between processors is executed by ISIN. Furthermore, in case of breakdown of one processor, ISIN may transmit the message to other processors regarding its failure. 

Because, each reference to the memory in tightly coupled systems is using interconnection network there is some delay in implementing the instructions. To decrease the delay, each processor may make use of cache memory for frequent references prepared by the processor as shown in Figure.

1557_Interrupt Signal Interconnection Network (ISIN).png

Figure: Tightly coupled systems with cache memory

The shared-memory multiprocessor systems may further be splitted in three approaches that are based on the manner in which shared-memory is accessed. These modes are shown in Figure and are elucidated below.

1410_Interrupt Signal Interconnection Network (ISIN) 1.png

Figure: Modes of Tightly coupled systems


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