Illustration of instruction format, Computer Engineering

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Let's provide you a fundamental illustration by which you may be able to define the concept of instruction format. 

Let us consider the instruction format of a MIPS computer. MIPS is an abbreviation for Microprocessor without Interlocked Pipeline Stages. It's a microprocessor architecture created by MIPS Computer Systems Inc. most widely known for developing MIPS architecture. The MIPS CPU family was among most successful and flexible CPU designs throughout the 1990s. MIPS CPU has a 5-stage CPU pipeline to execute multiple instructions simultaneously. Now what we have introduced is a new term pipelining. What else: the 5 stage pipeline let's just introduce it here. It defines the five steps of execution of instructions which may be performed in an overlapped fashion. The below diagram will explain this concept: 

2480_ILLUSTRATION OF INSTRUCTION FORMAT.png

Figure: Pipeline

  • All stages are distinct and independent that is the second stage execution of Instruction 1 must not hinder Instruction 2.
  • Overall efficiency of system becomes better.

 


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