Hazards of pipeline - computer architecture, Computer Engineering

Hazards of pipeline - computer architecture:

Hazards: When a programmer (or compiler) writes assembly program code, they make the supposition that each instruction is executed before execution of the subsequent instruction is started. This supposition is invalidated by pipelining. When it causes a program to behave not correctly, this situation is known as a hazard. many techniques for resolving hazards such as stalling exist and forwarding.

Non-pipeline architecture is not efficient because some CPU components (modules) are idle as another module is active at the time instruction cycle. Pipelining does not fully cancel out idle time in a CPU but building those modules work in parallel improves program execution considerably.

Processors having pipelining are organized inside into stages which can semi-independently work on distant jobs. Each stage is organized and connected into a 'chain' so each stage's output is fed to another stage till the job is done. This organization of the processor permits overall processing time to be considerably reduced.

A deeper pipeline means that there are more stages in the pipeline, and so, fewer logic gates in each pipeline. It usually means that the processor's frequency may be increased as the cycle time is lowered. It happens due to the reason of fewer components in each stage of the pipeline; as a result the propagation delay is decreased for the whole stage.

Unluckily, not all of the instructions are independent. In a pipeline, finishing an instruction may need 5 stages. To operate at complete performance, this pipeline will required to run 4 subsequent independent instructions as the first is completing. If four instructions that do not depend on the output of the initial instruction are not available, the pipeline control logic has to insert a stall or wasted clock cycle into the pipeline till the dependency is resolved. Luckily, techniques like forwarding can considerably reduce the cases where stalling is needed. Whereas pipelining may in theory increase performance on a un pipelined core by a factor of the number of stages (presumptuous the clock frequency also scales with the number of stages), in fact, most of the code does not permit for ideal execution.

Posted Date: 10/13/2012 3:59:30 AM | Location : United States







Related Discussions:- Hazards of pipeline - computer architecture, Assignment Help, Ask Question on Hazards of pipeline - computer architecture, Get Answer, Expert's Help, Hazards of pipeline - computer architecture Discussions

Write discussion on Hazards of pipeline - computer architecture
Your posts are moderated
Related Questions
Determine the salient features of a parallel programmable interface, 8255. 24 I/O lines in 3 8-bit port groups - A, B, C A, B can be 8-bit input or output ports C

List the properties which a hashing function should possess to ensure a good search performance. What approaches are adopted to handle collision? A hashing function h must poss

What is Parsing? Parsing: It is the process of analyzing a text, made of an order of tokens, to find out its grammatical structure regarding a given formal grammar. Parsing

An ActiveX control has four types of properties: 1. Stock:-> These are standard properties supplied to each control, such as font / color. The developer must activate stock pro

PROCEDURE TO CREATE PROJECT IN COLLABORATION SYSTEM

Q. Illustrate working of Synchronous Counters? The main drawback of ripple counter is delay in changing the value. How? To understand this let's take a case when state of rippl

Q. What are the types of parallel programming? There are various parallel programming models in general use. A few of them are:  Data Parallel programming Message P

How to increase simulation speed     First figure out what is eating away your CPU cycles. Is it 1. Compile time - Use a Make file to compile only files with changes and not


Fail-first - artificial intelligence: Alternatively one such dynamic ordering procedure is known like "fail-first forward checking". In fact the idea is to take advantage of i