Hazards of pipeline - computer architecture:
Hazards: When a programmer (or compiler) writes assembly program code, they make the supposition that each instruction is executed before execution of the subsequent instruction is started. This supposition is invalidated by pipelining. When it causes a program to behave not correctly, this situation is known as a hazard. many techniques for resolving hazards such as stalling exist and forwarding.
Non-pipeline architecture is not efficient because some CPU components (modules) are idle as another module is active at the time instruction cycle. Pipelining does not fully cancel out idle time in a CPU but building those modules work in parallel improves program execution considerably.
Processors having pipelining are organized inside into stages which can semi-independently work on distant jobs. Each stage is organized and connected into a 'chain' so each stage's output is fed to another stage till the job is done. This organization of the processor permits overall processing time to be considerably reduced.
A deeper pipeline means that there are more stages in the pipeline, and so, fewer logic gates in each pipeline. It usually means that the processor's frequency may be increased as the cycle time is lowered. It happens due to the reason of fewer components in each stage of the pipeline; as a result the propagation delay is decreased for the whole stage.
Unluckily, not all of the instructions are independent. In a pipeline, finishing an instruction may need 5 stages. To operate at complete performance, this pipeline will required to run 4 subsequent independent instructions as the first is completing. If four instructions that do not depend on the output of the initial instruction are not available, the pipeline control logic has to insert a stall or wasted clock cycle into the pipeline till the dependency is resolved. Luckily, techniques like forwarding can considerably reduce the cases where stalling is needed. Whereas pipelining may in theory increase performance on a un pipelined core by a factor of the number of stages (presumptuous the clock frequency also scales with the number of stages), in fact, most of the code does not permit for ideal execution.