Handlers classification, Computer Engineering

Handler's Classification

In 1977, Wolfgang Handler proposed an detailed notation for expressing the parallelism and pipelining of computers. Handler's classification addresses the computer at three distinct stages:

  • Processor control unit (PCU),
  • Bit-level circuit (BLC),
  • Arithmetic logic unit (ALU),

Theprocessor control unit corresponds to a processor or CPU, the BLC corresponds to the logic circuit needed to perform one- bit operations in the ALU and the arithmetic logic unit corresponds to a functional unit or a processing element.

Handler's classification uses the following three pairs of integers to explain a computer: Computer = (p * p', a * a', b * b')

Whereas, p = number of PCUs

Whereas, p'= number of PCUs that can be pipelined

Whereas, a = number of ALUs controlled by each PCU

Where a'= number of ALUs that can be pipelined

Whereas, b = number of bits in ALU or processing element (PE) word

Whereas, b'= number of pipeline segments on all ALUs or in a single PE

The following operators and rules are used to show the relationship between a variety of elements of the computer:

  • The '*' operator is used to indicate that the units are pipelined or macro-pipelined with a stream of data running through all the units.
  • The '+' operator is used to denote that the units are not pipelined but work on independent streams of data.
  • The 'v' operator is used to denote that the computer hardware can work in one of numerous modes.
  • The '~' symbol is used to specify a range of values for any one of the parameters.
  • Peripheral processors are given away before the main processor using another three pairs of integers. If the given value of the second element of any pair is 1, it may misplaced for brevity.

Handler's classification is the best elaborate by showing how the operators and rules are used to classify numerous machines.

The CDC 6600 has only a single main processor supported by 10 I/O processors. One control unit managed one ALU with a 60-bit word length. The ALU has 10 functional units which can be produced into a pipeline. The 10 peripheral I/O processors may work in parallel with the CPU and with each other also. Every  I/O processor contains one 12-bit ALU. The explanation for the 10 I/O processors is:

                      CDC 6600I/O = (10, 1, 12)

The explanation for the main processor is:

                      CDC 6600main = (1, 1 * 10, 60)

The I/O processors and the main processor can be regarded as forming a macro-pipeline so the '*' operator is used to join the two structures:

CDC 6600 =  (central processor) *(I/O processors) =  (10, 1, 12) * (1, 1 * 10, 60)

Texas Instrument's Advanced Scientific Computer (ASC) have one controller coordinating four arithmetic units. Every arithmetic unit is an eight stage pipeline with 64-bit words. Therefore, we have:

                                    ASC = (1, 4, 64 * 8)

The Cray-1 is a 64-bit single processor computer whose ALU has twelve functional units, eight of which can be joined together to from a pipeline. Dissimilar functional units have from 1 to 14 segments, which can be pipelined also. Handler's description of the Cray-1 is:

                                   Cray-1 =  (1, 12 * 8, 64 * (1 ~ 14))

One more sample system is Carnegie-Mellon University's C.mmp multiprocessor. This system was considered to facilitate research into parallel computer architectures and consequently can be broadly reconfigured. The system exists of 16 PDP-11 'minicomputers' (which has a 16-bit word length), interrelated by a crossbar switching network. Usually, the C.mmp operates in MIMD mode for which the explanation is (16, 1, 16). It can also managed in SIMD mode, where all the processors are synchronized by a single master controller. The SIMD mode description is (1, 16, 16). At last, the system can be rearranged to manage in MISD mode. Here the processors are orderly arranged in a chain with a one  stream of data passing through all of them. The MISD modes description is (1 * 16, 1, 16). The 'v' operator is used to join descriptions of the same part of hardware operating in differing modes. Thus, Handler's description for the total C.mmp is:

                     C.mmp = (16, 1, 16) v (1, 16, 16) v (1 * 16, 1, 16)


The '+'  and '*'operators are used to join several separate pieces of hardware. The 'v' operator is of a dissimilar form to the other two in that it is used to join the different operating modes of a one piece of hardware.

While Flynn's classification is simple to use, Handler's classification is cumbersome. The straight use of numbers in the nomenclature of Handler's classification's build it much more abstract and hence hard. Handler's classification is extremely geared towards the description of chains and pipelines. While it is well able to explain the parallelism in a single processor, the range of parallelism in multiprocessor computers is not addressed well.

Posted Date: 3/1/2013 6:50:39 AM | Location : United States

Related Discussions:- Handlers classification, Assignment Help, Ask Question on Handlers classification, Get Answer, Expert's Help, Handlers classification Discussions

Write discussion on Handlers classification
Your posts are moderated
Related Questions
Overlay Graph: It overlay the content of two graphs that shares an ordinary x-axis. Left Y-axis on the merged graph show's the present graph's value & Right Y-axis illustrate the v

What is the length of function code at user-command? Every menu function, push button, or function key has an associated function code of length FOUR (for example, FREE), which

Each student will be assigned a binary system. The experimental references and the conditions are indicated in the table below. The student should make use of software available on

What is the maximum number of fragments that can result from a single IP Datagram? Explain. To fragment a datagram for transmission across a network, a router utilizes the netw

Salient points about addressing mode are:  This addressing mode is employed to initialise value of a variable. Benefit of this mode is that no extra memory accesses are

The aim of this project is for you to construct a fully working compiler for a small simple programming language, SPL. The compiler will read in SPL source code and produce ANSI C

How many select lines will a 16 to 1 multiplexer will have ?   Ans. For 16 to 1 MUX four select lines will be needed to select 16 (2 4 ) inputs.

How does TCP achieve reliability? One of the most significant technologies is retransmission. While TCP stands data the sender compensates for packet loss through implementing

Double Negation - Artificial intelligence: Always parents are correcting their children for the use of double negatives, but we have to be very alert with them in natural langu

State the datatypes of Verilog Verilog. Compared to VHDL, Verilog data types are very simple, easy to use and very much geared towards modeling hardware structure as opposed to