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In this segment, we will give very brief details of registers of a RISC system known as MIPS.
MIPS is a register-to-register or load/store architecture and employs three address instructions for data manipulation. It is due to register-register operands that you can have more operands in an instruction of 32 bits because register address are smaller.
MIPS have 32 addressable registers = 25
⇒ 5 bits register address.
Table given below shows MIPS general purpose registers.
MIPS register names start with a $. There are two naming conventions:
$0 $1 $2 ... $31
$a0 - $a3 $t0 - $t7 $s0 - $s7 $gp $fp $sp $ra
Not all of these are general-purpose registers. The subsequent table explains how each general register is treated and actions you can take with each one of the registers.
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