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Format of Control Register
The format for the control register is given in Figure. Bit 0 of this register might be one before data may be output and bit two might be one before data can be received. Programmed answering of a modem is accomplished by setting bit 1 to 1 since this forces the DTR pin to zero and the complement of DTR is usually linked to the CD line from the modem. Bit 3 equal to 1 force TxD to 0, thus causing break characters to be transmitted. Setting bit 4 to 1 causes every error bits in the status register to be cleared (the bits that are set when overrun, framing and parity errors occur). Bit 5 is utilized for sending a Request to send signal to a modem. If the complement of the RTS pin is linked to a modem's CA line, then a one put in bit5 will cause the CA line to go high. Setting bit 6 causes the8251 A to be reinitialized and the reset sequence to be re-entered (for instance a return is made to the top of the flowchart shown in Figure and the next output will be to the mode register). Bit seven is utilized just with the synchronous mode. When set, it causes the 8251A to start a bit-by-bit search for a sync character or sync characters.
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