Explain the 8259 microprocessor.
8259:
The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. This can be expanded to 64 interrupt requests with using one master 8259A and 8 slave units. CS and WR should be decoded. Other connections are direct to microprocessor. The workings of pins are given here:
Pins D7 to D0: bidirectional data connection pins,
IR7 to IR0: Interrupt request, utilized to request an interrupt and connect to a slave in a system along with multiple 8259A.
WR: It connects to a write strobe signal (upper or lower in a 16 bit system) ,
RD: It connects to the IORC signal,
INT: it Connects to the INTR pin on the microprocessor by the master and it is connected to a IR pin on a slave and
INTA: It connects to the INTA pin on the microprocessor. Within a system only the master INTA signal is associated
A0: it selects different command words along with in the 8259A,
CS: Chip select - It enables the 8259A for programming and control,
SP/EN: Slave Program (that is 1 for master, 0 for slave)/Enable Buffer (as controls the data bus transceivers into a large microprocessor based system while in buffered mode) and
CAS2-CAS0: It used as outputs from the master to the slaves in cascaded systems.
Figure: 8259 Block Diagram