Draw and elucidate the block diagram of programmable interrupt controller 8259.

The 8259A adds 8 vectored priority encoded interrupts to microprocessor. It can be expanded to 64 interrupt requests by employing one master 8259A and 8 slave units. CS and WR should be decoded. Other connections are direct to microprocessor. 

Pins D7 - D0: bidirectional data connection, IR7 - IR0: Interrupt request, used to request an interrupt and connect to a slave in a system with multiple 8259A.

WR :-Connects to a write strobe signal (upper or lower in a 16 bit system) ,  RD :- Connects to IORC signal ,  INT :- Connects to INTR pin on the microprocessor from master and is connected to a IR pin on a slave  and  INTA :- Connects to INTA pin on the microprocessor.  In a system only master INTA signal is connected A0:- Selects different command words with in 8259A, CS: - Chip select - enables 8259A for control andprogramming, SP/EN: - Slave Program (1 for master, 0 for slave)/Enable Buffer (controls data bus transceivers in a large microprocessor based system when in buffered mode) and CAS2-CAS0:- Used as outputs from master to the slaves in cascaded systems. 

 

Posted Date: 8/20/2013 2:35:02 AM | Location : United States

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