Different models of computation-parallel algorithms, Computer Networking

There are various computational models for representing the parallel computers. In this part, we discuss various models. These models would give a platform for the designing as well as the analysis of the parallel algorithms.

Combinational Circuits

Combinational Circuit is one of the forms for parallel computers. In interconnection networks, many processors communicate with each other directly and do not need a shared memory in between. Mostly, combinational circuit (cc) is a connected arrangement of logic gates with a set of m input lines and a set of n output lines as given in Figure. The combinational circuits are mostly made up of various interconnected components arranged in the form called as stages as given in Figure.

587_Combinational circuit.png

                                                                          Combinational circuit

2413_Detailed combinational circuit.png

Detailed combinational circuit

It might be noted here that there is no feedback control employed in combinational circuits. There are a small number of terminologies followed in the context of combinational circuits such as fan in and fan out. Fan in indicates the number of input lines attached to each device and fan out indicates the number of output lines. In Figure , the fan in is 3 and fan out is also 3. The following parameters are used for analyzing a combinational circuit:

1)  Depth: It means that the total number of phases used in the combinational circuit starting from the input lines to the output lines. For example, in the depth are 4, as there are four different phases attached to a interconnection network. The other form of interpretation of depth can be that it represents the worst case time complexity of resolving a problem as input is given at the initial input lines and data is transmitted between various phases through the interconnection network and at the end reaches the output lines.

2) Width: It represents the total number of devices attached for a particular phase. For example in Figure, there are 4 components linked to the interconnection network. It means that the width is 4.

3)  Size: It represents the total count of devices used in the complete combinational circuit. For example, in Figure , the size of combinational circuit is 16 i.e. (width * depth).

Posted Date: 3/2/2013 6:31:57 AM | Location : United States







Related Discussions:- Different models of computation-parallel algorithms, Assignment Help, Ask Question on Different models of computation-parallel algorithms, Get Answer, Expert's Help, Different models of computation-parallel algorithms Discussions

Write discussion on Different models of computation-parallel algorithms
Your posts are moderated
Related Questions
Q. What is Bipolar Encoding? - Uses three voltage levels negative, positive and zero - Zero level represents binary 0; 1s are represented with alternating positive and negat

Q. What are the trends in Network Security ? Trends in Network Security Improved vigilance for virus infections Continual maturation of firewall technologies

Differentiate between Web and Web Page Web or Net The World Wide Web (a server) consisting of a hypermedia system (linking sounds, text, pictures, video) that the com


Has a central core conductor covered in an insulating sheath encased in an outer conductor of metal foil  RG numbers indicate physical specs such as thickness and type of insula

Q. Describe the Hardware complexity of Benz Network? Hardware complexity of Benz Network:  Benz network employs lesser switches and it gives good connectivity. To come across h

Q. Illustrate Nonboundary-Level Masking with example? Nonboundary-Level Masking Example IP address 45 123 21 8 Mask 255 192 0 0 Subnet 45 64 0 0 123 0

Q. Illustrate Go Back - N protocol? Go Back - N - Sender window size - Receiver window size = 1 - Why the names go back- N? - When the frame is spoilt the sende

THICK ETHERNET WIRING:  It needs thick coax cable. AUI cable joins from NIC to transceiver. AUI cable take digital signal from NIC to transceiver. The transceiver creates anal

master construct #include extern float average(float,float,float); void master_construct ( float* x, float* xold, int n, float tol )  { int c, i, toobig; floa