Design a 4:1 mux in Verilog

 

Multiple styles of coding. e.g.

Using if-else statements

if(sel_1 == 0 && sel_0 == 0) output = I0;

else if(sel_1 == 0 && sel_0 == 1) output = I1;

else if(sel_1 == 1 && sel_0 == 0) output = I2;

else if(sel_1 == 1 && sel_0 == 1) output = I3;

Using case statement

case ({sel_1, sel_0})

00 : output = I0;

01 : output = I1;

10 : output = I2;

11 : output = I3;

default : output = I0;

endcase

 

 

Posted Date: 9/17/2013 12:55:01 AM | Location : United States

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