Cross section of nmos with channel formed: on state, Electrical Engineering

Cross Section of NMOS with Channel Formed: ON state

A metal-oxide-semiconductor field-effect transistor (MOSFET) is based upon the modulation of charge concentration through a MOS capacitance in between a body electrode and a gate electrode situated above the body and insulated from all another device regions by a gate dielectric layer that in the case of a MOSFET (metal-oxide-semiconductor field-effect transistor) is an oxide, like silicon dioxide. If dielectrics other than an oxide like silicon dioxide (often considered to as oxide) are used the device might be referred to as a metal-insulator-semiconductor FET (MISFET). As Compared to the MOS capacitor, the MOSFET involves two additional terminals (source and drain), each one of them are connected to individual highly doped regions which are separated by the body region. These regions can be either p or n type, but they have to be both be of similar type, and of opposite type to the body region. The source and drain (not like the body) are highly doped as signified by a '+' sign after the type of doping.

If the MOSFET is an n-channel or nMOS FET, after that the source and drain are 'n+' regions and the body is a 'p' region. As explained above, with sufficient gate voltage, holes from the body are driven away from the gate, making an inversion layer or n-channel at the interface in between the p region and the oxide. This conducting channel extends among the source and the drain, and current is conducted via it while a voltage is applied between source and drain.

For gate voltages less than the threshold value, the channel is lightly populated, and just only an extremely small sub threshold leakage current can flow in between the source and the drain.

If the MOSFET is a p-channel or PMOS FET, after that the source and drain are 'p+' regions and the body is a 'n' region. While a negative gate-source voltage (positive source-gate) is applied, it makes a p-channel at the surface of the n region, analogous to the n-channel case, but along with opposite polarities of charges and voltages. While a voltage less negative than as compared to the threshold value (a negative voltage for p-channel) is applied in between gate and source, the channel disappears and just only a very small sub threshold current can flow in between the source and the drain.

The source is so named since it is the source of the charge carriers (electrons for n-channel, holes for p-channel) which flow through the channel; likewise, the drain is where the charge carriers leave the channel.

The device may have Silicon on Insulator (SOI) device where a Buried Oxide (BOX) is formed below a thin semiconductor layer. If the channel region in between the gate dielectric and a Buried Oxide (BOX) region is extremely thin, the very thin channel region is considered to as an Ultra Thin Channel (UTC) region along with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. On the other hand, the device may have a Semi conductor On Insulator (SEMOI) device in which semiconductors other than silicon are used. Several alternative semiconductor materials may be used. While the source and drain regions are made above the channel in whole or in part, they are referred to as Raised Source/Drain (RSD) regions.

Posted Date: 1/11/2013 1:16:32 AM | Location : United States







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