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Q. Concurrently read concurrently write?
It is one of the models derived from PRAM. In this model the processors access the memory locations simultaneously for reading and writing operations. In this algorithm that uses CRCW model of computation, n3 number of processors is used. Whenever a simultaneous write operation is executed on a particular memory location let's say m than there are odds of occurrence of a conflict. So the write conflicts it implies that (WR, RW, WW) have been resolved in the subsequent manner. In a condition when more than one processor attempts to write on same memory location, the value stored in memory location is always the sum of values computed by different processors.
Algorithm Matrix Multiplication using CRCW
Input// Two Matrices M1 and M2
For I=1 to n //Operation performed in PARALLEL
For j=1 to n //Operation performed in PARALLEL
For k=1 to n //Operation performed in PARALLEL
Oij = 0;
Oij = M1ik * M2kj
End For
The complexity of CRCW based algorithm is O(1).
What is WMFC? WMFC if the control signals that causes the processor's control circuitry to wait for the arrival of the MFC signal.
Q. Example on hamming error correcting code? For illustration a 4-bit matching word can stand for 2 4 =16 values that range from 0 to 15 as: 0000, 0001, 0010, 0011, 0100, 01
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