Array processing, Computer Engineering

Array Processing

We have seen that for performing vector operations, the pipelining concept has been taken. There is another method for vector operations. If we have an array of n processing elements (PEs) i.e., multiple ALUs for storing many operands of the vector, then an n instruction, for example, vector addition, is broadcast to all PEs such that they add all                                            

Operands of the vector at the similar time. It means all PEs will present computation in parallel. All PEs are synchronized under one control unit. This organization of synchronous array of PEs for vector operations is known as Array Processor. The organization is similar as in SIMD which we studied in unit 2. An array processor can handle single instruction multiple data streams as we have seen earlier in case of SIMD organization. Thus, array processors are also known as SIMD array computers.

The organization of an array processor is given in Figure. The following components are organized in an array processor:

                                     47_Array Processing.png

                                                              Organisation of SIMD Array Processor

Posted Date: 3/4/2013 5:20:05 AM | Location : United States







Related Discussions:- Array processing, Assignment Help, Ask Question on Array processing, Get Answer, Expert's Help, Array processing Discussions

Write discussion on Array processing
Your posts are moderated
Related Questions

Explain Classification Based On Grain Size This categorization is based on distinguishing the parallelism in a program to be executed on a multiprocessor system. The concept is

Define memory management system? The part of the computer system that supervises the flow of information among auxiliary memory and main memory is known as memory management sy

Q. Show Sample Instruction Format of MIPS instruction? Early MIPS architectures had 32-bit instructions and later versions have 64-bit implementations. The first commercial


Host Computer:  An array processor may be attached to a host computer by the control unit. The reason of the host computer is to broadcast a sequence of vector instructions by CU t

There can be more than one node at the highest level in the structure. False.  One can describe only single node at the highest level in the structure on LDB

What are the four necessary conditions of deadlock prevention? Four essential conditions for deadlock prevention are: 1.  Removing  the  mutual  exclusion  condition  implie

Q. Displaying the List of Files with DIR? You can display the list of files kept in a diskette or hard disk with the DIR commend. This Commends list files and sub directories i

a. Explain the hardware mechanism for handling multiple interrupt requests. b. What are handshaking signals? Describe the handshake control of data transfer during input and out