We have seen that for performing vector operations, the pipelining concept has been taken. There is another method for vector operations. If we have an array of n processing elements (PEs) i.e., multiple ALUs for storing many operands of the vector, then an n instruction, for example, vector addition, is broadcast to all PEs such that they add all
Operands of the vector at the similar time. It means all PEs will present computation in parallel. All PEs are synchronized under one control unit. This organization of synchronous array of PEs for vector operations is known as Array Processor. The organization is similar as in SIMD which we studied in unit 2. An array processor can handle single instruction multiple data streams as we have seen earlier in case of SIMD organization. Thus, array processors are also known as SIMD array computers.
The organization of an array processor is given in Figure. The following components are organized in an array processor:
Organisation of SIMD Array Processor