Address phase timing - computer architecture, Computer Engineering

Address phase timing:

On the rising edge of clock 0, the initiator notes IRDY # and FRAME# both high, and GNT# low, so it drives the command, address and asserts FRAME# in time for the rising edge of c lock 1. Targets latch the address and start decoding it. They can respond having DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, by seeing no other response by clock 4, may respond on clock5. If the master does not observe a response by clock 5, it will dismiss the transaction and remove FRAME# on clock 6.


2223_Address phase timing.png

TRDY# and STOP# are deserted (high) during the address phase. The initiator can assert IRDY# as soon as it is prepared to transfer data, which could theoretically beat the time clock 2.


Any particular device on a PCI bus that is capable of acting as a bus master can initiate a transaction having any other device. To ensure that only 1 transaction is initiated at a time, each master have to wait first for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a distant request line REQ# that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no present requests. The arbiter can remove GNT# at any particular time. A device which loses GNT# may complete its existing transaction, but may not begin one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it start.

The arbiter can also provide GNT# at any particular time, by including during another master's transaction. At the time of transaction, either FRAME# or IRDY# or both are asserted; when both are deserted, the bus is id le. A device can initiate a transaction at any time that GNT# is asserted and the bus is idle.



Posted Date: 10/13/2012 7:32:41 AM | Location : United States

Related Discussions:- Address phase timing - computer architecture, Assignment Help, Ask Question on Address phase timing - computer architecture, Get Answer, Expert's Help, Address phase timing - computer architecture Discussions

Write discussion on Address phase timing - computer architecture
Your posts are moderated
Related Questions
Explain the significance of different fields of an instruction An instruction is a command given to a computer to perform a particular operation on some given data and the form

Q. Catch output from child tasks? int pvm_catchout( FILE *ff ) Catch output from child tasks. ff is file descriptor on which we write collected output. The defau

Which of the fastest logic: TTL, ECL, CMOS and LSI ? Ans. The fastest logic family of all logic families ECL. High  speeds  are  possible  in  ECL  since the  transistors  a

Subtraction of 01000-01001 using 2's complement method. Ans. Firstly 1's complement of 01001 is 10110 and 2's complement is 10110+ 1 =10111. Thus   01000 =  01000 - 01001

Q. What is Gantt chart and Kiviat diagram? Gantt chart: Gantt chart explains numerous activities of every processor with respect to progress in time in busy -overhead - id

Explain about Behavioral Notations These notations contain dynamic elements of the model.  Their elements comprise interaction and the state machine. It also comprise classe

Basic Concept of Data Parallelism Thinking the condition where the same problem of submission of „electricity bill? is Handled as follows: Again, three are counters. Howeve

A design for the seven segment decoder is required. The decoder has four inputs which represent a number from 0 to 9 in binary and seven outputs which are connected to the seven

The Extensible Firmware Interface (EFI) is a specification that defines a software interface among an operating system and platform firmware. EFI is intended as a significantly imp

What is the use of boot block? For a computer to start running when powered up or rebooted it needs to have an initial program to run. This bootstrap program tends to be simple