Address phase timing - computer architecture, Computer Engineering

Address phase timing:

On the rising edge of clock 0, the initiator notes IRDY # and FRAME# both high, and GNT# low, so it drives the command, address and asserts FRAME# in time for the rising edge of c lock 1. Targets latch the address and start decoding it. They can respond having DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, by seeing no other response by clock 4, may respond on clock5. If the master does not observe a response by clock 5, it will dismiss the transaction and remove FRAME# on clock 6.

 

2223_Address phase timing.png

TRDY# and STOP# are deserted (high) during the address phase. The initiator can assert IRDY# as soon as it is prepared to transfer data, which could theoretically beat the time clock 2.

Arbitration:

Any particular device on a PCI bus that is capable of acting as a bus master can initiate a transaction having any other device. To ensure that only 1 transaction is initiated at a time, each master have to wait first for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a distant request line REQ# that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no present requests. The arbiter can remove GNT# at any particular time. A device which loses GNT# may complete its existing transaction, but may not begin one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it start.

The arbiter can also provide GNT# at any particular time, by including during another master's transaction. At the time of transaction, either FRAME# or IRDY# or both are asserted; when both are deserted, the bus is id le. A device can initiate a transaction at any time that GNT# is asserted and the bus is idle.

 

 

Posted Date: 10/13/2012 7:32:41 AM | Location : United States







Related Discussions:- Address phase timing - computer architecture, Assignment Help, Ask Question on Address phase timing - computer architecture, Get Answer, Expert's Help, Address phase timing - computer architecture Discussions

Write discussion on Address phase timing - computer architecture
Your posts are moderated
Related Questions
Device drivers are special programs installed by config.sys file to control installable devices.  So personal computers can be expanded at some future time by installation of new d

State the importance of CRT monitor CRT is considered to be one of the most important component because the quality of displayed image influences the perception of generated de

There are situations, called hazards that stop the next instruction in the instruction stream from implementing during its designated clock cycle. Hazards decrease the performance

Write a program to mask bits D3D2D1D0 and to set bits D5D4 and to invert bits D7D6 of the AX register.

Give the decription of user case A use case is a description of the set of the sequence of actions which a system performs to produce an observable result which is of a value t

Explain the product lifecycle in an Operating System

Assignment 3.b: Experiment with Neural Network Background: In this assignment, you will experiment with neural network for solving different types of practical problems. Y

The hexadecimal number for (95.5) 10 is ? Ans. (95.5) 10 = (5F.8) 16 Integer part Fractional part 0.5x16=8.0


Q. What you mean by organizational effectiveness? Organizational effectiveness is measured in terms of productivity, structural flexibility, Employee involvement and Job satisf