Address phase - computer architecture, Computer Engineering

Address phase:

A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the AD[31:0] lines, the associated command (for example: I/O write or memory read,) on the C/BE[3:0]# lines, and pulls FRAME# low.

Each other device inspect the address and command & decides whether to respond as the target by asserting DEVSEL#. Device has to respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within one or two cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (In fact, the time to respond is 2.5 cycles, since PCI devices have to transmit all signals half a cycle early so that they can be retaining3 cycles later.)Note that a device have to latch the address on the first cycle; the initiator is needed to remove the address and command from the bus on the following cycle, even before retaining a DEVSEL# response. The extra time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is permitted for some address ranges. It is generally used by an ISA bus bridge for addresses within its particular range (16 bits for I/O and 24 bits for memory).

On the sixth cycle, if there has been no response, the initiator can abort the transaction by deserting FRAME#. It is known as master abort termination and it is customary for PCI bus bridges to return all- ones data (0xFFFFFFFF) in this particular case. PCI devices therefore are generally designed to ignore by using the all-ones value in essential status registers, so that such type of error may be easily detected by software.


Posted Date: 10/13/2012 7:29:10 AM | Location : United States

Related Discussions:- Address phase - computer architecture, Assignment Help, Ask Question on Address phase - computer architecture, Get Answer, Expert's Help, Address phase - computer architecture Discussions

Write discussion on Address phase - computer architecture
Your posts are moderated
Related Questions
Explain The do while loops The do while loops is similar, but the test occurs after the loop body is executed. This ensures that the loop body is run at least once.

Q. The work function of a metal surface is 6.626 X 10-19 joule. Compute the frequency of the radiation? Work function                                     W = hγ o The fre

Pruning - artificial intelligence: Recall which pruning a search space means deciding that there certain branches to should not be explored. Moreover if an agent knows for sur

Define the Character Set of C Language? C uses the lower case letter a to z, the upper case letters A to Z, the digits 0 to 9 and certain characters as building blocks to form

Concept of Multithreading: These troubles increase in the design of large-scale multiprocessors such as MPP as discussed above. Thus, a solution for optimizing this latency should

A three stage network is realized by using switching matrices of size p x s in stage 1, r x r matrices in stage 2 and s x p matrices in stage 3. Using the Lee's probability graph s

I am required to write about the impact of the internet on firms with reference to the following questions: 1. Describe the concept of value creation. Explain how a firm can use

General Concepts of links and association A link is a conceptual or physical connection among objects for instance. Mathematically, you can define a link as a tuple which is a

Write a program to find the area under the curve y = f(x) between x = a and x = b, integrate y = f(x) between the limits of a and b

What is MMX Technology MMX Technology: MMX (Multimedia extensions) technology adds 57 new instructions to instruction set of Pentium - 4 microprocessors. MMX technology also