Address phase - computer architecture, Computer Engineering

Assignment Help:

Address phase:

A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the AD[31:0] lines, the associated command (for example: I/O write or memory read,) on the C/BE[3:0]# lines, and pulls FRAME# low.

Each other device inspect the address and command & decides whether to respond as the target by asserting DEVSEL#. Device has to respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within one or two cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (In fact, the time to respond is 2.5 cycles, since PCI devices have to transmit all signals half a cycle early so that they can be retaining3 cycles later.)Note that a device have to latch the address on the first cycle; the initiator is needed to remove the address and command from the bus on the following cycle, even before retaining a DEVSEL# response. The extra time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is permitted for some address ranges. It is generally used by an ISA bus bridge for addresses within its particular range (16 bits for I/O and 24 bits for memory).

On the sixth cycle, if there has been no response, the initiator can abort the transaction by deserting FRAME#. It is known as master abort termination and it is customary for PCI bus bridges to return all- ones data (0xFFFFFFFF) in this particular case. PCI devices therefore are generally designed to ignore by using the all-ones value in essential status registers, so that such type of error may be easily detected by software.


Related Discussions:- Address phase - computer architecture

Existential elimination, Existential Elimination : Now we have a sente...

Existential Elimination : Now we have a sentence, A, is with an  existentially quantified variable, v, so then just for every constant symbol k, that it does not appear anywhe

Examples of artificial neural networks, Examples of artificial neural netwo...

Examples of artificial neural networks: Now here as an example consider a ANN that has been trained to learn the following rule categorising the brightness of 2x2 black and wh

Multiple instruction and multiple data stream (mimd), Multiple Instruction ...

Multiple Instruction and Multiple Data stream (MIMD): In this categorization, numerous processing elements and multiple control units are ordered as in MISD. However the differ

Explain deadlock, What is a deadlock? A deadlock is a situation that ca...

What is a deadlock? A deadlock is a situation that can increase when two units, A and B use a shared resource. Assume that unit B cannot complete its task unless unit A complet

Show the responsibilities of session layer, Q. Show the Responsibilities of...

Q. Show the Responsibilities of session layer? Session layer: Main functions of this layer are to establish, synchronize and maintain the interaction between two communicatio

Illustrate about the single inheritance, Illustrate about the single inheri...

Illustrate about the single inheritance During inheritance, superclass feature may by override by a subclass defining that feature with the same name. The overriding features (

Describe independent loops in fortran, Q. Describe Independent Loops in for...

Q. Describe Independent Loops in fortran? HPF offers extra opportunities for parallel execution by employing the INDEPENDENT directive to declare the iterations of a do-loop is

Explain the storage class register, The Storage Class register The Sto...

The Storage Class register The Storage Class register : The storage class 'register' tells the compiler that the associated variable  should  be stored  in  high-speed  memor

How can we set the table spaces and extent sizes, How can we set the table ...

How can we set the table spaces and extent sizes? You can state the extent sizes and the table space (physical storage area in the database) in which a transparent table is to

Write Your Message!

Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd