Address phase - computer architecture, Computer Engineering

Address phase:

A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the AD[31:0] lines, the associated command (for example: I/O write or memory read,) on the C/BE[3:0]# lines, and pulls FRAME# low.

Each other device inspect the address and command & decides whether to respond as the target by asserting DEVSEL#. Device has to respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within one or two cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (In fact, the time to respond is 2.5 cycles, since PCI devices have to transmit all signals half a cycle early so that they can be retaining3 cycles later.)Note that a device have to latch the address on the first cycle; the initiator is needed to remove the address and command from the bus on the following cycle, even before retaining a DEVSEL# response. The extra time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is permitted for some address ranges. It is generally used by an ISA bus bridge for addresses within its particular range (16 bits for I/O and 24 bits for memory).

On the sixth cycle, if there has been no response, the initiator can abort the transaction by deserting FRAME#. It is known as master abort termination and it is customary for PCI bus bridges to return all- ones data (0xFFFFFFFF) in this particular case. PCI devices therefore are generally designed to ignore by using the all-ones value in essential status registers, so that such type of error may be easily detected by software.

 

Posted Date: 10/13/2012 7:29:10 AM | Location : United States







Related Discussions:- Address phase - computer architecture, Assignment Help, Ask Question on Address phase - computer architecture, Get Answer, Expert's Help, Address phase - computer architecture Discussions

Write discussion on Address phase - computer architecture
Your posts are moderated
Related Questions
Token packets in universal serial bus - computer architecture: Token packets consist of a PID byte followed by two payload bytes: a 5-bit CRC and 11 bits of address. Tokens

does matlab contain procedures for knoledge representation? if yes where can i find it?

How exceptions are handled in java? Exception handing In Java: A java exception is an object which describes an exceptional condition which has occurred in a piece of code.

A logic gate is an electronic circuit that generates a typical output signal which depends on its input signal. Output signal of a gate is a general boolean operation of its input

Microsoft access name has been transformed to Microsoft office access. This software incorporates relational database management system which joins GUI (graphical user interface) w

Q. What is a virtual address? Von Neumann had suggested that execution of a program is possible only if program and data are residing in memory. In such a condition program len

Define the meaning of business-to-business. B2B (business-to-business): The consensus is universal: it is the priority; it is where the money is. It’s rather true; theref

How music is produced and generated - CAD Computer software and hardware advances have changed how music is produced and generated. Some of the primary reasons for this have

What is WAP? WAP is stands for Wireless Application Protocol. It is a global, open standard which gives mobile users access to Internet services by handled devices. Wireless A

Which two properties are on every validation control?  Two properties are:- a) Control to validate b) Error Message.