Reference no: EM131274143
Assignment
A. Consider a computer memory whose logical address is thirty two bits (4 bytes) and page is of 4K size.
1) Use a picture to how the translation process from logical address to physical address.
2) If we use single level page table, how many bits for page offset and how many bits for page number?
3) If we use two levels for page table, draw a diagram to show your design.
B. For page replacement, suppose we have the reference list 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6, use FIFO, optimal, and LRU to show how many page faults in each method.
C. Discuss the difference between external and internal fragmentation.
D. Discuss the advantages and disadvantages of large page size vs. small page size.
E. Why is frequency of page usage a poor measure for reducing future page faults?
F. Which page-replacement strategy incurs more execution overhead: least recent used (LRU) or least frequently used (LFU)?
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