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A workstation utilizes a 15-MHZ processor with a claimed 10-MIPS rating to implement a provided programme mix. Suppose a one-cycle delay for every memory access.
1) What is effective CPI of this computer?
2) Processor is being upgraded with the 30-MHZ clock. However speed of the memory subsystem remains unchanged and consequently two clock cycles are required per memory access. If 30% of the instruction needed one memory access & another 5% required two memory access per instruction, what is the performance of the upgraded processor with a compatible instruction set and equal instruction counts?
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