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An inhibited toggle flip-flop has inputs I0, I1, T, and Reset, and outputs Q and QN. Reset is active high and overrides the action of the other inputs. The flip-flop works as follows. If I0 = ‘1', the flip-flop changes state on the rising edge of T; if I1 = ‘1', the flip-flop changes state on the falling edge of T. If I0 = I1 = ‘0', no state change occurs (except on reset).Assume the propagation delay from T to output is 8 ns and from reset to output is 5 ns.
(a) Write a complete VHDL description of this flip-flop.
(b) Write a sequence of simulator commands that will test the flip-flop for the input sequence I1 = ‘1', toggle T twice, I1 = ‘0', I0 = ‘1', toggle T twice.
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