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We need to use asynchronous TDM and combine 50 digital sources. On average only 20% of the sources are active at any time. Each output slot carries 18 bits of data from each digital source. Also 8 extra bits are added to each frame for synchronization. The output rate measurement shows a rate of 2Gbps. Answer the following:
A) how many slots are in each frame
b) what is the size of an output frame (in bits)?
c) calculate the throughput at the output link
d) what is the rate of each input channel (in bps)?
e) the efficiency of this TDM multiplexing?
The outputs of two "NAND" gates are connected to the inputs of an "Exclusive Or" gate. Each of the "NAND" gates has one input at a logic high level, and the other input at a logic low level. What is the output of the "Exclusive Or" gate?
Apple A5 die size is 122mm^2 when fabricated in 45nm technology. Assume they purchase 300mm wafers at a foundry for $ 2.5K /wafer. Assume a yield of 70%. What is Apple's approximate die cost?
Invesitagtion of Intermodulation through an amplifier, An amplifier is designed to handle frequencies around 9 GHz. The bandwidth of the amplifier is 2 GHz with a center frequency of 9 GHz
An experiment consists of tossing a fair coin four times in succession. What are the possible outcomes Now count up the number of outcomes with three heads. If the outcomes are equally probable, what is the probability of three heads
In comparing the behaviour of an n-channel MOSFET with a p-channel device having identical geometry and threshold voltage, it is found that the n-channel FET has a greater drain current than that of the p-channel FET.
draw a combinational logic circuit (using AND, OR, etc.) that implements the function. (Note: x is a multiple of 3 if x=i*3 for some integer i.)
Using many resistors and the DMM, try to determine what digits each colour band represents. Briefly explain your method and your findings in the space below.
Important information about Frequency Divider, Design a frequency divider circuit that will output three pulse frequencies: 25 kHz, 10kHz, and 2.5kHz. Assume that only a 150 kHz CMOS compatible signal is available for the divider input
A digital communications system is being designed with the goal of transmitting 32 kbits/s over a channel having a bandwidth of 8 kHz. Determine (a) the number of encoding levels required and (b) the minimum signal-to-noise ratio required in the c..
generated by a loud speaker is reflected at two different walls with reflection coefficients r1 and r2. the signal x(t) recorded by amicrophone close to the loud speaker, after sampling is
A series circuit has a DC voltage source (56 volts), a resistor, (72 ohms), a capacitor (82 farads), and a switch. The capacitor is initially uncharged and the switch closes at t=0.
explain the function of frequency dial and frequency range.
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