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A 20 kVA, 2000/200 V, 50 Hz transformer is operated at no-load on rated voltage, the input being 150 W at 0.12 power factor. When it is operating at rated load, the voltage drops in the total leakage reactance and the total resistance are, respectively, 2 and 1 per cent of the rated voltage. Determine the input power and power factor when the transformer delivers 10 kW at 200 V at 0.8 pf lagging to a load on the LV side.
A three phase load draws 100kW at a poer factor of 0.7 laggaing from a 220V line to line. In parallel with this load is a three phase capacitor bank which draws 60kVAR. Find the total line current and the resultant power factor.
Write a sequence of instructions to initialize and run the timer to geneate an 800 baud rate clock. what would be the baud rate if the intial value of the timer was set to 9AH
what will happen to the negative terminal if ground is applied to the positive terminal of an inverting op-amp?
Calculate the output resistance of the device, dIC/dVC, for 0
Find I using in network in network figure.- Nodal analysis - Mesh analysis - Superposition - Thevenin theorem - Norton theorem
The manufacturer of commercial jets has a cost index equal to 94.9 per aircraft in 2009. the anticipated cost index for the airplane in 2014 is 106.8. the avaerage compound rate of growth should hold steady for the next 15 years.
A computer has 16-bit instructions and 64 registers. Suppose it is required to have at least 14 instructions designed to have 2 operands from registers (e.g., add, $1, $3 puts the sum of $1 and $3 into $1.
A sample has a T2 of 50 ms. The net magnetization is rotated into the xy-plane and allowed to decay. how much transverse magnetization will be present 20 ms after being placed in the plane
A system has the transfer function: g(s)=7(9) / s(s^2 +(7+9) s + 7(9) a). write this transfer function in polynomial form and pole-zero form.
Determine the largest permissible value of P for the beam and loading shown, knowing that the allowable normal stress is +8 ksi in tension and -18 ksi in compression.
The counter will use the falling edge of the clock (denoted by Clk) and have a separte reset pin (R) which will reset the counnter to 0000 when it is low (e.g. R=0). Please use D type flip-flops. write down the state diagram , and state table.
Design and implement an algorithm that determines whether or not a given array of elements, list1, is completely contained within another given array of elements, list2. Consider two different scenarios: 1) both arrays are sorted; 2) both arrays a..
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