"INTERCONNECTION METHODSThe problem consists of meeting all the customer requirements while maintaining theeconomics of large volume production. This is quickly solved by marketing two kinds ofproducts. One had been the standard circuits like the NAND gates, inverters, shift registers,etc. Different methods were proposed by different manufacturers. Some of these methods used are as follows:1) The Discretionary Wiring approach of Texas Instruments which is based on the economiesof increased yield of a circuit.2) The Micromatrix approach of Fairchild which is based on maximizing the standardnumber of production steps for LSI chips, thus achieving the economies of batch production.3) The Polycell approach of Motorola which use Computer Aided Design (CAD) togetherwith the batch production techniques as mentioned earlier.4) Other approaches: There are other approaches proposed by different manufacturers whichhave yet to gain a wide popularity.Let us discuss all methods in Detail:-1) DISCRETIONARY WIRING APPROACH OF TEXAS INSTRUMENTS:-In using this approach a chip has been produced with more devices etched on it than haverequired for the logic function. On this chip,the first level of metallization had been doneirrespective of whether the devices had some defect or not. At appropriate placesmetallic pads were also deposited to carry out multi-probe tests. The result of this the test will indicate the good and bad cells on the chip. This information together withthe functional requirement of the chip has been then fed to a computer. Using this data, acomputer program then generates the required information for the second and thethird levels of metalization.But this process tohas many Disadvantages:(1) The effective density of devices on the chip has been reduced. This is due to two factors - the requirement of test pads and the etching of redundant devices on the chip.(2) Even though the first level of metallization has been tested the second and thirdthe level of metallization may also have faults resulting in a rejected chip.(3) The computer program for the second and third level masks must be able tohandle all the different device configurations on the first level. B. MICROMATRIX APPROACH OF FAIRCHILDThis approach have specific example of Master Slice Fixed Interconnection Pattern (MasterSlice FIP) method. In this approach, the circuits share all the masks except for those involvedin metallization. Figure 14 shows a conceptual diagram of this scheme in which there arecertain areas reserved for cells and others reserved for interconnection. These are calledvertical and horizontal channels. The Micromatrix the approach consists of chips with arraysof cells having different functions (like NAND gates, FF's, etc.). These arrays are chosen sothat they can satisfy a given customer requirement. The arrays are prefabricated and stocked.Prefabrication allows batch production. Thus the assembly line can be studied and volumes ofdata can be gathered to predict reliability and failure mode. When a customer requests adesign, the design is analyzed and an appropriate chip with an array of cells is chosen. Pads for input/output are then allocated and the first level metallization is designed. On top of thislayer, an insulating layer is required before the second level of metallization can be made.Vias (holes in the insulation layer to connect the first and second level of metallization) areselected and a second level metallization pattern designed. All this is done by a designer anda draftsman using special design layout sheets. After the layout is completed the artwork isused to make a set of photolithographic plates to produce the required masks.C. POLYCELL APPROACH OF MOTOROLAThis approach exploits Computer Aided Design (CAD) method to lay out the interconnectionpatterns for LSI chips. Initially, a library of cell designs is maintained inside a computermemory. These cells are commercially called Polycells by Motorola. The Polycell inventoryis changed as new designs are encountered. When a custom design is required a designengineer analyzes the requirements and, with the use of a display and teletypecommunicatewith the computer. He can select differently Polycells to be laid out on a chip and displaythem if required. Simultaneously, data structures are generated inside the computer to depictthe layout of the cells. When the design is finished the computer can generate instructions foran automatic drafting machine to prepare the complete set of mask masters for the array.Figure 15, taken from Khambata (1968), shows the design steps in the polycell approach.The outstanding advantage of this scheme is the great flexibility that a designer has inchoosing the polycells by interaction with the computer. Due to CAD the turnaround time isminimized. An optimum design can be accomplished by the computer keeps track of thecomplexities which, if designed by a human, would present a formidable task.' Besides, acustomer can define his own Polycells, which, if proprietary information can be guarded veryeasily. For a particular design, there is a possibility of combining two or more Polycells to achieve power reduction, the increment in speed or higher density or other such advantages.Even though computer time is costly, changes in design are not formidable and are easy tomake. The designs could also be checked exhaustively by the computer before fabrication.The entire above points make the Polycell approach the most attractive of the threedescribed. If Motorola can deliver all that is claimed in the above approach, then this schemewould be the most reliable and economical to use. "