CMOS NOR Gate:

Figure (f) depicts the CMOS NOR Gate where the T_N1 and T_P1 has the same Input 1 and T_N2 and T_P2 has the same Input 2. When Input 1 = Input 2 = 1, T_N1 and T_N2 is on and T_P1 and T_P1 are off. Hence the output is at 0 V. When Input 1 = Input 2 = 0, T_N1 and T_N2 is off and T_P1 and T_P1 are on. Therefore the output is at V_cc. For the case while one of the inputs is 1, one of the NMOS FET shall be on and therefore the output will be at 0 V. Therefore the CMOS circuit of Figure (f) behaves as a NOR Gate.