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CMOS NOR Gate:
Figure (f) depicts the CMOS NOR Gate where the TN1 and TP1 has the same Input 1 and TN2 and TP2 has the same Input 2. When Input 1 = Input 2 = 1, TN1 and TN2 is on and TP1 and TP1 are off. Hence the output is at 0 V. When Input 1 = Input 2 = 0, TN1 and TN2 is off and TP1 and TP1 are on. Therefore the output is at Vcc. For the case while one of the inputs is 1, one of the NMOS FET shall be on and therefore the output will be at 0 V. Therefore the CMOS circuit of Figure (f) behaves as a NOR Gate.
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