Translation Look aside Buffer
In a cached system, the base addresses of the last few indexed pages is maintained in registers named the TLB that adds in faster lookup. TLB has those page-table entries that have been most currently used. Usually, every virtual memory instance gives 2 physical memory accesses-- one to get appropriate page-table entry, and one to get the defined data. Using TLB in-between, this is reduced to single physical memory access in forms of TLB-hit.