Sr flip-flop, Electrical Engineering

SR FLIP-FLOP (SRFF)

The symbol for the SRFF is shown in Figure (a), in which S stands for "set," R stands for "reset" on the input side, and there are two outputs, the normal output Q and the complementary output ¯Q. The operation of the SRFF can be understood by the following four basic rules.

1. If S = 1 and R = 0, then Q = 1 regardless of past history. This is known as the set condition.

2. If S = 0 and R = 1, then Q = 0 regardless of past history. This is known as the reset condition.

3. If S = 0 and R = 0, then Q does not change and stays at its previous value. This is a highly stable input condition.

4. The inputs S = 1 and R = 1 are not allowed (i.e., forbidden) because Q¯Q = 11; ¯Q is no longer complementary to Q. This is an unacceptable output state. Such a meaningless instruction should not be used. Figure (b) summarizes the specification for an SRFF in terms of a truth table, in which Qn is the state of the circuit before a clock pulse and Qn+1 is the state of the circuit following a clock pulse.

665_SR flip-flop.png

Posted Date: 6/24/2013 3:17:18 AM | Location : United States







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