Performance of pipelines with stalls, Computer Engineering

Performance of Pipelines with Stalls:

A stall is reason of the pipeline performance to degrade the ideal performance.

                                            Average instruction time un pipelined

Speedup from pipelining   =   ----------------------------------------

                                             Average instruction time pipelined

 

                                                    CPI un pipelined * Clock Cycle Time unpipelined

                                                = -------------------------------------

                                                     CPI pipelined * Clock Cycle Time pipelined

The ideal CPI on a pipelined machine is approximately always 1. Therefore, the pipelined CPI is CP I pipelined = Ideal CPI + Pipeline stall clock cycles per instruction

                            = 1 + Pipeline stall clock cycles per instruction

If we avoid the cycle time overhead of pipelining and suppose the stages are all perfectly balanced, then the cycle time of the 2 machines are equal and

 

                  CPI un pipelined

Speedup = ----------------------------

                  1+ Pipeline stall cycles per instruction

 

If all of the instructions take the similar number of cycles, which ought to be equal the number of pipeline stages (the depth of the pipeline) then un pipelined CPI is equivalent to the depth of the pipeline, leading to

 

                   Pipeline depth

Speedup = --------------------------

                  1 + Pipeline stall cycles per instruction

 

If there are no pipeline stalls, it leads to the intuitive result that pipelining can developed performance by the depth of pipeline.

 

Posted Date: 10/13/2012 4:33:31 AM | Location : United States







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